1. Field of the Invention
The present invention relates to the generation of trace signals within a data processing apparatus having one or more components whose behaviour is to be traced.
2. Description of the Prior Art
Tracing the activity of a data processing system whereby a trace stream is generated including data representing the step-by-step activity within the system is a highly useful tool in system development. However, with the general move towards more deeply embedded processor cores, it becomes more difficult to track the state of the processor core via externally accessible pins. Accordingly, as well as off-chip tracing mechanisms for capturing and analysing trace data, increased amounts of tracing functionality are being placed on-chip. An example of such on-chip tracing mechanisms is the Embedded Trace Macrocell (ETM) provided by ARM Limited, Cambridge, England, in association with various of their ARM processors.
Such tracing mechanisms produce in real time a trace stream of data representing activities of the data processing system that are desired to be traced. This trace stream can then subsequently be used to facilitate debugging of sequences of processing instructions being executed by the data processing system.
It is known to provide tracing mechanisms incorporating trigger points that serve to control the tracing operation, such as starting or stopping tracing upon access to a particular register, address or data value. Such mechanisms are very useful for diagnosing specific parts of a system or types of behaviour.
However, as data processing systems increase in complexity, it is clear that there is potentially a very large amount of information that could be traced. Typically the stream of trace data that is generated by the ETM is buffered prior to output for subsequent analysis, and accordingly there is the potential for bursts of trace data to cause that buffer to overflow, thereby resulting in loss of trace data. For example, in a typical implementation, all of the trace data generated by the ETM may be written immediately to an internal First-In-First-Out (FIFO) buffer, and then subsequently drained through a relatively narrow bandwidth trace port to a trace buffer. When a broad spectrum of behaviour of the data processing apparatus is being traced, it is possible that bursts of trace data can cause the FIFO to overflow, leading to loss of trace data.
One known technique for seeking to combat this problem is to arrange the ETM to output a signal to the component whose behaviour is being traced when the fullness of the FIFO reaches a predetermined level, this signal then causing the component to stall with the aim of allowing the FIFO to drain before an overflow occurs. However, the use of such a signal has proved difficult to implement in practice, since it requires action to be taken externally to the ETM (i.e. by the component being traced) to seek to avoid overflow of the FIFO. It will be appreciated that there is an inherent latency between the ETM issuing such a signal, and that signal being actioned by the component being traced, for example a processor core, and during that latency period, further activities of that component will continue to be traced, and may cause the FIFO to overflow in any event.
Accordingly, it will be desirable to provide an improved technique for seeking to reduce the likelihood of loss of trace data.